C8051F70X_0910 Datasheet, PDF (23/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
CIP-51 8051
Controller Core
C2CK/RST
Power On
Reset
Reset
Debug /
Programming
Hardware
C2D
Peripheral Power
8 kB Flash Memory
256 Byte RAM
256 Byte XRAM
32 Bytes EEPROM
(‘F712/13 Only)
VDD
GND
Regulator
SYSCLK
Core Power
XTAL1
XTAL2
Precision
Internal
Oscillator
External
Clock
Circuit
System Clock
Configuration
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART
Timers 0,
1, 2, 4
Timer 3 /
RTC
PCA
Priority
Crossbar
Decoder
SPI
WDT
SMBus
Crossbar Control
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
...
Port 3
Drivers
...
Port 4
Drivers
...
Port 5
Drivers
...
Port 6
Drivers
...
Analog Peripherals
Capacitive
Sense
+
-
Comparator
VDD
VREF
(‘F712/14 Only)
10-bit
A
500 ksps
ADC
M
U
X
VDD
Temp Sensor
P0.0 / VREF
P0.1 / AGND
P0.2 / XTAL1
P0.3 / XTAL2
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P2.0
P2.7
P3.0
P3.7
P4.0
P4.3
P5.0
P5.7
P6.0
P6.5
Figure 1.6. C8051F712/13/14/15 Block Diagram
Rev. 0.3
23