C8051F70X_0910 Datasheet, PDF (260/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
31.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines
the Timer 3 operation mode.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal high-frequency oscillator drives the system clock while Timer 3 is clocked by an external oscillator
source. The external oscillator source divided by 8 is synchronized with the system clock when in all oper-
ating modes except suspend. When the internal oscillator is placed in suspend mode, The external clock/8
signal can directly drive the timer. This allows the use of an external clock to wake up the device from sus-
pend mode. The timer will continue to run in suspend mode and count up. When the timer overflow occurs,
the device will wake from suspend mode, and begin executing code again. The timer value may be set
prior to entering suspend, to overflow in the desired amount of time (number of clocks) to wake the device.
If a wake-up source other than the timer wakes the device from suspend mode, it may take up to three
timer clocks before the timer registers can be read or written. During this time, the STSYNC bit in register
OSCICN will be set to 1, to indicate that it is not safe to read or write the timer registers.
31.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 31.7,
and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled
and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L)
overflow from 0xFF to 0x00.
T3XCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL
10
SYSCLK / 12
External Clock / 8
0
1
SYSCLK
0
TR3
1
To ADC
TCLK
TMR3L
TMR3H
TMR3RLL TMR3RLH
Reload
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK
Figure 31.7. Timer 3 16-Bit Mode Block Diagram
Interrupt
260
Rev. 0.3