C8051F70X_0910 Datasheet, PDF (159/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 25.3. OSCICN: Internal H-F Oscillator Control
Bit
7
6
5
4
3
2
Name ^{IOSCEN IFRDY SUSPEND STSYNC}
SSE
Type
R/W
R
R/W
R
R/W
R
Reset
1
1
0
0
0
0
1
0
IFCN[1:0]
R/W
0
0
SFR Address = 0xA9; SFR Page = F
Bit Name
Function
7 IOSCEN Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
6
IFRDY Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
5 SUSPEND Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
4 STSYNC Suspend Timer Synchronization Bit.
This bit is used to indicate when it is safe to read and write the registers associated
with the suspend wake-up timer. If a suspend wake-up source other than Timer 3
has brought the oscillator out of suspend mode, it make take up to three timer clocks
before the timer can be read or written.
0: Timer 3 registers can be read safely.
1: Timer 3 register reads and writes should not be performed.
3
SSE
Spread Spectrum Enable.
Spread spectrum enable bit.
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
2
Unused Read = 0b; Write = Don’t Care
1:0 IFCN[1:0] Internal H-F Oscillator Frequency Divider Control Bits.
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
Rev. 0.3
159