C8051F70X_0910 Datasheet, PDF (27/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Table 3.1. Pin Definitions for the C8051F70x/71x (Continued)
Name
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
64-Pin 48-Pin Type
Packages Packages
Description
48
35
D I/O or Port 0.7.
A In
47
34
D I/O or Port 1.0.
A In
46
33
D I/O or Port 1.1.
A In
45
32
D I/O or Port 1.2.
A In
44
31
D I/O or Port 1.3.
A In
43
D I/O or Port 1.4.
A In
42
D I/O or Port 1.5.
A In
39
D I/O or Port 1.6.
A In
38
D I/O or Port 1.7.
A In
37
29
D I/O or Port 2.0.
A In Cap Sense input pin 1.
36
28
D I/O or Port 2.1.
A In Cap Sense input pin 2.
35
27
D I/O or Port 2.2.
A In Cap Sense input pin 3.
34
26
D I/O or Port 2.3.
A In Cap Sense input pin 4.
33
25
D I/O or Port 2.4.
A In Cap Sense input pin 5.
32
24
D I/O or Port 2.5.
A In Cap Sense input pin 6.
31
23
D I/O or Port 2.6.
A In Cap Sense input pin 7.
30
22
D I/O or Port 2.7.
A In Cap Sense input pin 8.
Rev. 0.3
27