C8051F70X_0910 Datasheet, PDF (37/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

6. QFN-48 Package Specifications
C8051F70x/71x
Figure 6.1. QFN-48 Package Drawing
Table 6.1. QFN-48 Package Dimensions
Dimension
A
A1
b
D
D2
e
E
Min
Nom
Max
0.80
0.90
1.00
0.00
—
0.05
0.18
0.23
0.30
7.00 BSC.
3.90
4.00
4.10
0.50 BSC.
7.00 BSC.
Dimension Min
Nom
Max
E2
3.90
4.00
4.10
L
0.30
0.40
0.50
L1
0.00
—
0.10
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.05
ddd
—
—
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. 3.This drawing conforms to JEDEC outline MO-220, variation VKKD-4 except for features D2 and
L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 0.3
37