C8051F70X_0910 Datasheet, PDF (29/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Table 3.1. Pin Definitions for the C8051F70x/71x (Continued)
Name
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
64-Pin 48-Pin Type
Packages Packages
Description
10
10
D I/O or Port 5.0.
A In Cap Sense input pin 26.
7
7
D I/O or Port 5.2.
A In Cap Sense input pin 27
6
6
D I/O or Port 5.3.
A In Cap Sense input pin 28.
5
5
D I/O or Port 5.4.
A In Cap Sense input pin 29.
4
4
D I/O or Port 5.5.
A In Cap Sense input pin 30.
3
3
D I/O or Port 5.6.
A In Cap Sense input pin 31.
2
2
D I/O or Port 5.7.
A In Cap Sense input pin 32.
1
D I/O Port 6.0.
64
D I/O Port 6.1.
63
D I/O Port 6.2.
62
1
D I/O Port 6.3.
61
48
D I/O Port 6.4.
60
47
D I/O Port 6.5.
Rev. 0.3
29