C8051F70X_0910 Datasheet, PDF (279/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 32.2. PCA0MD: PCA Mode
Bit
7
6
5
4
3
2
1
0
Name ^CIDL
CPS2
CPS1
CPS0
ECF
Type
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xED; SFR Page = F
Bit Name
Function
7
CIDL PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6:4 Unused Read = 000b, Write = don't care.
3:1 CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
110-111: Reserved
0
ECF PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Rev. 0.3
279