C8051F70X_0910 Datasheet, PDF (77/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 13.2. CS0CF: Capacitive Sense Configuration
Bit
7
6
5
4
3
Name
CS0CM[2:0]
Type
R
R/W
R/W
R/W
R
Reset
0
0
0
0
0
2
1
0
CS0ACU[1:0]
R
R/W
R/W
0
0
0
SFR Address = 0x9E; SFR Page = 0
Bit
Name
Description
7
Unused ^{Read = 0b; Write = Don’t care}
6:4 CS0CM[2:0] CS0 Start of Conversion Mode Select.
000: Conversion initiated on every write of 1 to CS0BUSY.
001: Conversion initiated on overflow of Timer 0.
010: Conversion initiated on overflow of Timer 2.
011: Conversion initiated on overflow of Timer 1.
100: Conversion initiated on overflow of Timer 3.
101: Reserved.
110: Conversion initiated continuously after writing 1 to CS0BUSY.
111: Auto-scan enabled, conversions initiated continuously after writing 1 to
CS0BUSY.
3:2
Unused Read = 00b; Write = Don’t care
1:0 CS0ACU[1:0] CS0 Accumulator Mode Select.
00: Accumulate 1 sample.
01: Accumulate 4 samples.
10: Accumulate 8 samples.
11: Accumulate 16 samples.
Rev. 0.3
77