C8051F70X_0910 Datasheet, PDF (180/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 26.11. P0DRV: Port 0 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
P0DRV[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF9; SFR Page = F
Bit
Name
Function
7:0 P0DRV[7:0] Drive Strength Configuration Bits for P0.7-P0.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P0.n Output has low output drive strength.
1: Corresponding P0.n Output has high output drive strength.
SFR Definition 26.12. P1: Port 1
Bit
7
6
5
4
3
2
1
0
Name
P1[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0x90; SFR Page = All Pages; Bit Addressable
Bit Name
Description
Write
7:0 P1[7:0] Port 1 Data.
0: Set output latch to logic
Sets the Port latch logic
LOW.
value or reads the Port pin ^{1: Set output latch to logic}
logic state in Port cells con- ^HIGH.
figured for digital I/O.
Read
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
180
Rev. 0.3