C8051F70X_0910 Datasheet, PDF (97/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
16.2. Configuring the External Memory Interface
Configuring the External Memory Interface consists of five steps:
1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is
most common).
2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic 1).
3. Select Multiplexed mode or Non-multiplexed mode.
4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or
off-chip only).
5. Set up timing to interface with off-chip memory or peripherals.
Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed
mode selection, and Mode bits are located in the EMI0CF register shown in SFR Definition .
16.3. Port Configuration
The EMIF pinout is shown in Figure 16.2 on Page 112
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches for those pins. See Section “26. Port Input/Output” on page 165 for more
information about Port operation and configuration. The Port latches should be explicitly configured to
“park” the External Memory Interface pins in a dormant state, most commonly by setting them to a
logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv-
ers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configured for push-pull mode.
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