C8051F70X_0910 Datasheet, PDF (183/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 26.17. P2: Port 2
Bit
7
6
5
4
3
2
1
0
Name
P2[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xA0; SFR Page = All Pages; Bit Addressable
Bit Name
Description
Write
7:0 P2[7:0] Port 2 Data.
0: Set output latch to logic
Sets the Port latch logic
LOW.
value or reads the Port pin ^{1: Set output latch to logic}
logic state in Port cells con- ^HIGH.
figured for digital I/O.
Read
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
SFR Definition 26.18. P2MDIN: Port 2 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P2MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF3; SFR Page = F
Bit
Name
Function
7:0 P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
Rev. 0.3
183