C8051F70X_0910 Datasheet, PDF (43/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Table 7.9. EEPROM Electrical Characteristics
V_DD = 1.8 to 3.6 V; T_A = –40 to +85 °C unless otherwise specified. Use factory-calibrated settings.
Parameter
Conditions
Min
Typ
Write to EEPROM from RAM
Read of EEPROM to RAM
Endurance (Writes)
TBD
TBD
3.0
50 x T_SYSCLK
TBD
Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
Max
TBD
TBD
—
Units
ms
µs
cycles
Table 7.10. ADC0 Electrical Characteristics
V_DD = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
DC Accuracy
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Full Scale Error
Offset Temperature Coefficient
Guaranteed Monotonic
10
bits
—
±0.5
±1
LSB
—
±0.5
±1
LSB
–2
0
2
LSB
–2
0
2
LSB
—
45
— ppm/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
56
60
—
dB
Total Harmonic Distortion
Up to the 5th harmonic
—
72
—
dB
Spurious-Free Dynamic Range
—
–75
—
dB
Conversion Rate
SAR Conversion Clock
Conversion Time in SAR Clocks
Track/Hold Acquisition Time
Throughput Rate
10-bit Mode
8-bit Mode
V_DD >= 2.0 V
V_DD < 2.0 V
—
—
8.33 MHz
13
—
— clocks
11
—
— clocks
300
—
—
ns
2.0
—
—
µs
—
—
500 ksps
Analog Inputs
ADC Input Voltage Range
Sampling Capacitance
Input Multiplexer Impedance
1x Gain
0.5x Gain
0
— VREF
V
—
5
—
pF
—
3
—
pF
—
5
—
k
Power Specifications
Power Supply Current
Power Supply Rejection
Operating Mode, 500 ksps
—
600 TBD
µA
—
–70
—
dB
Rev. 0.3
43