C8051F70X_0910 Datasheet, PDF (262/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
31.3.3. Comparator 0 Capture Mode
The capture mode in Timer 3 allows Comparator 0 rising edges to be captured with the timer clocking from
the system clock or the system clock divided by 12. Timer 3 capture mode is enabled by setting TF3CEN
to 1 and T3SPLIT to 0.
When capture mode is enabled, a capture event will be generated on every Comparator 0 rising edge.
When the capture event occurs, the contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3
reload registers (TMR3RLH:TMR3RLL) and the TF3H flag is set (triggering an interrupt if Timer 3 inter-
rupts are enabled). By recording the difference between two successive timer capture values, the
Comparator 0 period can be determined with respect to the Timer 3 clock. The Timer 3 clock should be
much faster than the capture clock to achieve an accurate reading.
This mode allows software to determine the time between consecutive Comparator 0 rising edges, which
can be used for detecting changes in the capacitance of a capacitive switch, or measuring the frequency of
a low-level analog signal.
T3XCLK
SYSCLK / 12
0
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
External Clock / 8
1
SYSCLK
0
TR3
TCLK _{TMR3L TMR3H}
1
Capture
Comparator 0
Output
TF3CEN
TMR3RLL TMR3RLH
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK
Figure 31.9. Timer 3 Capture Mode Block Diagram
Interrupt
262
Rev. 0.3