C8051F70X_0910 Datasheet, PDF (233/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SCK*
MISO
T_MCKH
T_MCKL
T
MIS
T
MIH
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 29.8. SPI Master Timing (CKPHA = 0)
SCK*
MISO
T_MCKH
T_MCKL
T
MIS
T
MIH
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 29.9. SPI Master Timing (CKPHA = 1)
Rev. 0.3
233