C8051F70X_0910 Datasheet, PDF (65/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
12. Comparator0
C8051F70x/71x devices include an on-chip programmable voltage comparator, Comparator0, shown in
Figure 12.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see
Section “26.4. Port I/O Initialization” on page 172). Comparator0 may also be used as a reset source (see
Section “23.5. Comparator0 Reset” on page 152).
The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section
“12.1. Comparator Multiplexer” on page 70.
CPT0CN
VDD
Comparator
Input Mux
CP0 +
+
CP0 - _-
GND
D ^SET Q
Q CLR
D ^SET Q
Q CLR
(SYNCHRONIZER)
CPT0MD
Reset
Decision
Tree
CP0
Crossbar
CP0A
CP0RIF
0
1
0
CP0FIF
1
CP0EN
EA
0
1
CP0
0 Interrupt
1
Figure 12.1. Comparator0 Functional Block Diagram
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “26.3. Priority Crossbar Decoder” on
page 170 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
Rev. 0.3
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