C8051F70X_0910 Datasheet, PDF (94/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
15.1. Program Memory
The members of the C8051F70x/71x device family contain 16 kB (C8051F702/3/6/7), 15 kB
(C8051F700/1/4/5), or 8 kB (C8051F708/9 and C8051F710/1/2/3/4/5) of re-programmable Flash memory
that can be used as non-volatile program or data storage. The last byte of user code space is used as the
security lock byte (0x3FFF on 16 kB devices, 0x3BFF on 15 kB devices and 0x1FFF on 8 kB devices).
C8051F702/3/6/7
Lock Byte
Lock Byte Page
0x3FFF
0x3FFE
0x3E00
Flash Memory Space
C8051F700/1/4/5
Lock Byte
Lock Byte Page
0x3BFF
0x3BFE
0x3A00
Flash Memory Space
C8051F708/9 and
C8051F710/1/2/3/4/5
Lock Byte
Lock Byte Page
0x1FFF
0x1FFE
0x1E00
Flash Memory Space
0x0000
0x0000
0x0000
Figure 15.2. Flash Program Memory Map
15.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F70x/71x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can
be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used to
read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access
feature provides a mechanism for the C8051F70x/71x to update program code and use the program mem-
ory space for non-volatile data storage. Refer to Section “20. Flash Memory” on page 133 for further
details.
15.2. EEPROM Memory
The C8051F700/1/4/5/8/9 and C8051F712/3 contain EEPROM emulation hardware, which uses Flash
memory to emulate a 32-byte EEPROM memory space for non-volatile data storage. The EEPROM data is
accessed through a RAM buffer for increased speed. More details about the EEPROM can be found in
Section “21. EEPROM” on page 140.
15.3. Data Memory
The C8051F70x/71x device family includes 512 bytes of RAM data memory. 256 bytes of this memory is
mapped into the internal RAM space of the 8051. 256 bytes of this memory is on-chip “external” memory.
The data memory map is shown in Figure 15.1 for reference.
15.3.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
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