C8051F70X_0910 Datasheet, PDF (40/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
7.2. Electrical Characteristics
Table 7.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Supply Voltage (Note 1)
Regulator in Normal Mode
Regulator in Bypass Mode
Digital Supply Current with
CPU Active (Normal Mode,
Note 2)
Digital Supply Current with
CPU Inactive (Idle Mode,
Note 2)
Digital Supply Current
(shutdown)
V_DD = 1.8 V, Clock = 25 MHz
V_DD = 1.8 V, Clock = 1 MHz
V_DD = 1.8 V, Clock = 32 kHz
V_DD = 3.0 V, Clock = 25 MHz
V_DD = 3.0 V, Clock = 1 MHz
V_DD = 3.0 V, Clock = 32 kHz
V_DD = 1.8 V, Clock = 25 MHz
V_DD = 1.8 V, Clock = 1 MHz
V_DD = 1.8 V, Clock = 32 kHz
V_DD = 3.0 V, Clock = 25 MHz
V_DD = 3.0 V, Clock = 1 MHz
V_DD = 3.0 V, Clock = 32 kHz
Oscillator not running (stop mode),
Internal Regulator Off
Oscillator not running (stop or suspend
mode), Internal Regulator On
Oscillator not running (stop or suspend
mode), Internal Regulator in Bypass
Digital Supply RAM Data
Retention Voltage
Specified Operating Tempera-
ture Range
SYSCLK (system clock
frequency)
(Note 3)
Tsysl (SYSCLK low time)
Tsysh (SYSCLK high time)
Min Typ Max Units
1.8 3.0 3.6 V
1.7 1.8 1.9 V
— 5.5 TBD mA
— 1.2 — mA
— 175 — µA
— 6.5 TBD mA
— 1.3 — mA
— 190 — µA
— 2.5 TBD mA
— 180 — µA
— 90 — µA
— 3.2 TBD mA
— 200 — µA
— 110 — µA
— TBD — µA
— 85 TBD µA
— 55 TBD µA
— TBD —
V
–40 — +85 °C
0
— 25 MHz
18 — — ns
18 — — ns
Notes:
1. Analog performance is not guaranteed when V_DD is below 1.8 V.
2. Includes bias current for internal voltage regulator.
3. SYSCLK must be at least 32 kHz to enable debugging.
4. Supply current parameters specified with Memory Power Controller enabled.
40
Rev. 0.3