C8051F70X_0910 Datasheet, PDF (155/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 24.1. WDTCN: Watchdog Timer Control
Bit
7
6
5
4
3
2
1
0
Name
WDT[7:0]
Type
R/W
Reset
0
0
0
1
0
1
1
1
SFR Address = 0xE3; SFR Page = All Pages
Bit
Name
Description
Write
Read
7:0 WDT[7:0] WDT Control.
Writing 0xA5 both
enables and reloads the
WDT.
Writing 0xDE followed
within 4 system clocks by
0xAD disables the WDT.
Writing 0xFF locks out
the disable feature.
4 WDTSTATUS Watchdog Status Bit.
0: WDT is inactive
1: WDT is active
2:0 WDTTIMEOUT Watchdog Timeout Interval WDTCN[2:0] bits set the
Bits.
Watchdog Timeout Inter-
val. When writing these
bits, WDTCN[7] must be
set to 0.
Rev. 0.3
155