C8051F70X_0910 Datasheet, PDF (234/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
NSS
T_SE
SCK*
T
CKH
T_CKL
T
SIS
T
SIH
MOSI
MISO
T
SEZ
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 29.10. SPI Slave Timing (CKPHA = 0)
T_SD
T
SDZ
NSS
T
T
T
SE
CKL
SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
SEZ
MISO
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SLH
T
SDZ
Figure 29.11. SPI Slave Timing (CKPHA = 1)
234
Rev. 0.3