C8051F70X_0910 Datasheet, PDF (93/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
15. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F70x/71x device family is shown in Figure 15.1
PROGRAM/DATA MEMORY
(FLASH)
0x3FFF
0x3FFE
C8051F702/3/6/7
Lock Byte
16 K Bytes FLASH
0x0000
(In-System
Programmable in 512
Byte Sectors)
0x3BFF
0x3BFE
C8051F700/1/4/5
Lock Byte
15 K Bytes FLASH
0x0000
(In-System
Programmable in 512
Byte Sectors)
0x1FFF
0x1FFE
C8051F708/9 and
C8051F710/1/2/3/4/5
Lock Byte
8 K Bytes FLASH
0x0000
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0xFFFF
EXTERNAL DATA ADDRESS SPACE
Same 256 bytes as from
0x0000 to 0x01FF, wrapped
on 256-byte boundaries
0x0100
0x00FF
0x0000
XRAM - 256 Bytes
(accessable using MOVX
instruction)
Figure 15.1. C8051F70x/71x Memory Map
Rev. 0.3
93