C8051F70X_0910 Datasheet, PDF (157/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 25.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
1
0
Name CLKRDY
CLKDIV[2:0]
Reserved
CLKSEL[2:0]
Type
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xBD; SFR Page= F
Bit Name
Function
7 CLKRDY System Clock Divider Clock Ready Flag.
0: The selected clock divide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
6:4 CLKDIV System Clock Divider Bits.
Selects the clock division to be applied to the selected source (internal or external).
000: Selected clock is divided by 1.
001: Selected clock is divided by 2.
010: Selected clock is divided by 4.
011: Selected clock is divided by 8.
100: Selected clock is divided by 16.
101: Selected clock is divided by 32.
110: Selected clock is divided by 64.
111: Selected clock is divided by 128.
3 Reserved Read = 0b. Must write 0b.
2:0 CLKSEL[2:0] System Clock Select.
Selects the oscillator to be used as the undivided system clock source.
000: Internal Oscillator
001: External Oscillator
All other values reserved.
Rev. 0.3
157