C8051F70X_0910 Datasheet, PDF (41/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Table 7.3. Port I/O DC Electrical Characteristics
V_DD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage
Current
Conditions
High Drive Strength
I_OH = –3 mA, Port I/O push-pull
I_OH = –10 µA, Port I/O push-pull
I_OH = –10 mA, Port I/O push-pull
Low Drive Strength
I_OH = –1 mA, Port I/O push-pull
I_OH = –10 µA, Port I/O push-pull
I_OH = –3 mA, Port I/O push-pull
High Drive Strength
I_OL = 8.5 mA
I_OL = 10 µA
I_OL = 25 mA
Low Drive Strength
I_OL = 1.4 mA
I_OL = 10 µA
I_OL = 4 mA
Weak Pullup Off
Weak Pullup On, V_IN = 0 V
Min
Typ
V_DD - 0.7
V_DD - 0.1
—
—
—
V_DD - 0.8
V_DD - 0.7
V_DD - 0.1
—
—
—
V_DD - 0.8
—
—
—
—
—
1.0
—
—
—
—
—
1.0
0.75 x V_DD
—
—
—
-1
—
—
25
Max
—
—
—
—
—
—
0.6
0.1
—
0.6
0.1
—
—
0.6
1
50
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
Table 7.4. Reset Electrical Characteristics
V_DD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
V_DD POR Ramp Time
V_DD Monitor Threshold (V_RST)
Missing Clock Detector
Timeout
Reset Time Delay
Minimum RST Low Time to
Generate a System Reset
V_DD Monitor Turn-on Time
V_DD Monitor Supply Current
Conditions
I_OL = 8.5 mA,
V_DD = 1.8 V to 3.6 V
RST = 0.0 V
Time from last system clock
rising edge to reset initiation
Delay between release of any
reset source and code
execution at location 0x0000
V_DD = V_RST - 0.1 V
Min
Typ
—
—
0.75 x V_DD —
—
—
—
25
—
—
1.7
1.75
TBD
500
—
TBD
15
—
—
TBD
—
25
Max Units
0.6
V
—
V
0.3 x V_DD V_DD
50
µA
1
ms
1.8
V
TBD
µs
TBD
µs
—
µs
—
µs
TBD
µA
Rev. 0.3
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