PIC24FJ256DA210 Datasheet, PDF (97/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
The CORCON register contains the IPL3 bit, which,
together with IPL<2:0>, indicates the current CPU
priority level. IPL3 is a read-only bit so that trap events
cannot be masked by the user software.
The interrupt controller has the Interrupt Controller Test
register, INTTREG, which displays the status of the
interrupt controller. When an interrupt request occurs,
it’s associated vector number and the new interrupt pri-
ority level are latched into INTTREG. This information
can be used to determine a specific interrupt source if
a generic ISR is used for multiple vectors (such as
when ISR remapping is used in bootloader applica-
tions) or to check if another interrupt is pending while in
an ISR.
All interrupt registers are described in Register 7-1
through Register 7-40 in the succeeding pages.
REGISTER 7-1: SR: ALU STATUS REGISTER (IN CPU)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0, HSC
—
—
—
—
—
—
—
DC⁽¹⁾
bit 15
bit 8
R/W-0, HSC
IPL2^(2,3)
bit 7
R/W-0, HSC R/W-0, HSC
IPL1^(2,3)
IPL0^(2,3)
R-0, HSC
RA⁽¹⁾
R/W-0, HSC
N⁽¹⁾
R/W-0, HSC
OV⁽¹⁾
R/W-0, HSC
Z⁽¹⁾
R/W-0, HSC
C⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
bit 7-5
Unimplemented: Read as ‘0’
IPL<2:0>: CPU Interrupt Priority Level Status bits^(2,3)
111 = CPU interrupt priority level is 7 (15); user interrupts are disabled
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
Note 1:
2:
3:
See Register 3-1 for the description of the remaining bits (bit 8, 4, 3, 2, 1 and 0) that are not dedicated to
interrupt control functions.
The IPL bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
 2010 Microchip Technology Inc.
DS39969B-page 97