PIC24FJ256DA210 Datasheet, PDF(348/408 Page) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

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PIC24FJ256DA210 Datasheet, PDF (348/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

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PIC24FJ256DA210 FAMILY

REGISTER 27-1: CW1: FLASH CONFIGURATION WORD 1

U-0

U-0

U-0

U-0

U-0

U-0

U-0

U-0

â

â

â

â

â

â

â

â

bit 23

bit 16

r-x

reserved

bit 15

R/PO-1

JTAGEN

R/PO-1

GCP

R/PO-1

GWRP

R/PO-1

DEBUG

r-1

reserved

R/PO-1

ICS1

R/PO-1

ICS0

bit 8

R/PO-1

FWDTEN

bit 7

R/PO-1

WINDIS

R/PO-1

ALTVREF(1)

R/PO-1

FWPSA

R/PO-1

WDTPS3

R/PO-1

WDTPS2

R/PO-1

WDTPS1

R/PO-1

WDTPS0

bit 0

Legend:

R = Readable bit

-n = Value at POR

r = Reserved bit

W = Writable bit

â1â = Bit is set

U = Unimplemented bit, read as â0â

â0â = Bit is cleared

x = Bit is unknown

bit 23-16

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9-8

bit 7

bit 6

bit 5

Unimplemented: Read as â1â

Reserved: The value is unknown; program as â0â

JTAGEN: JTAG Port Enable bit

1 = JTAG port is enabled

0 = JTAG port is disabled

GCP: General Segment Program Memory Code Protection bit

1 = Code protection is disabled

0 = Code protection is enabled for the entire program memory space

GWRP: General Segment Code Flash Write Protection bit

1 = Writes to program memory are allowed

0 = Writes to program memory are not allowed

DEBUG: Background Debugger Enable bit

1 = Device resets into Operational mode

0 = Device resets into Debug mode

Reserved: Always maintain as â1â

ICS<1:0>: Emulator Pin Placement Select bits

11 = Emulator functions are shared with PGEC1/PGED1

10 = Emulator functions are shared with PGEC2/PGED2

01 = Emulator functions are shared with PGEC3/PGED3

00 = Reserved; do not use

FWDTEN: Watchdog Timer Enable bit

1 = Watchdog Timer is enabled

0 = Watchdog Timer is disabled

WINDIS: Windowed Watchdog Timer Disable bit

1 = Standard Watchdog Timer is enabled

0 = Windowed Watchdog Timer is enabled; FWDTEN must be â1â

ALTVREF: Alternate VREF Pin Selection bit(1)

1 = VREF is on a default pin (VREF+ on RA10 and VREF- on RA9)

0 = VREF is on an alternate pin (VREF+ on RB0 and VREF- on RB1)

Note 1: Unimplemented in 64-pin devices, maintain at â1â (VREF+ on RB0 and VREF- on RB1).

DS39969B-page 348

ï£ 2010 Microchip Technology Inc.

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