PIC24FJ256DA210 Datasheet, PDF (273/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
19.0 ENHANCED PARALLEL
MASTER PORT (EPMP)
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 42. “Enhanced Parallel Master
Port (EPMP)” (DS39730). The informa-
tion in this data sheet supersedes the
information in the FRM.
The Enhanced Parallel Master Port (EPMP) module is
present in PIC24FJXXXDAX10 devices and not in
PIC24FJXXXDAX06 devices. The EPMP provides a
parallel 4-bit (Master mode only), 8-bit (Master and
Slave modes) or 16-bit (Master mode only) data bus
interface to communicate with off-chip modules, such
as memories, FIFOs, LCD controllers and other micro-
controllers. This module can serve as either the master
or the slave on the communication bus. For EPMP
Master modes, all external addresses are mapped into
the internal Extended Data Space (EDS). This is done
by allocating a region of the EDS for each chip select,
and then assigning each chip select to a particular
external resource, such as a memory or external con-
troller. This region should not be assigned to another
device resource, such as RAM or SFRs. To perform a
write or read on an external resource, the CPU should
simply perform a write or read within the address range
assigned for EPMP.
Note: The EPMP module is not present in 64-pin
devices (PIC24FJXXXDAX06).
The EPMP has an alternative master feature. The
graphics controller module can control the EPMP
directly in Alternate Master mode to access an external
graphics buffer.
TABLE 19-1:
Pin
RA14
RC4
RF12
RG6
RG7
RA3
RG8
RA4
ALTERNATE EPMP PINS
ALTPMP = 0
PMCS2
PMA22
PMA5
PMA18
PMA20
PMA4
PMA21
PMA3
Key features of the EPMP module are:
• Extended Data Space (EDS) interface allows
Direct Access from the CPU
• Up to 23 Programmable Address Lines
• Up to 2 Chip Select Lines
• Up to 2 Acknowledgement Lines (one per chip
select)
• 4-bit, 8-bit or 16-bit wide Data Bus
• Programmable Strobe Options (per chip select)
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
• Programmable Address/Data Multiplexing
• Programmable Address Wait States
• Programmable Data Wait States (per chip select)
• Programmable Polarity on Control Signals (per
chip select)
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
• Alternate Master feature
19.1 ALTPMP Setting
Many of the lower order EPMP address pins are shared
with ADC inputs. This is an untenable situation for
users that need both the ADC channels and the EPMP
bus. If the user does not need to use all the address
bits, then by clearing the ALTPMP (CW3<12>) Config-
uration bit, the lower order address bits can be mapped
to higher address pins, which frees the ADC channels.
ALTPMP = 1
PMA22
PMCS2
PMA18
PMA5
PMA4
PMA20
PMA3
PMA21
 2010 Microchip Technology Inc.
DS39969B-page 273