PIC24FJ256DA210 Datasheet, PDF (250/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
18.4.2
RECEIVING AN IN TOKEN IN
DEVICE MODE
1. Attach to a USB host and enumerate as described
in “Chapter 9 of the USB 2.0 Specification”.
2. Create a data buffer and populate it with the data
to send to the host.
3. In the appropriate (even or odd) TX BD for the
desired endpoint:
a) Set up the status register (BDnSTAT) with
the correct data toggle (DATA0/1) value and
the byte count of the data buffer.
b) Set up the address register (BDnADR) with
the starting address of the data buffer.
c) Set the UOWN bit of the status register to
‘1’.
4. When the USB module receives an IN token, it
automatically transmits the data in the buffer.
Upon completion, the module updates the status
register (BDnSTAT) and sets the Transfer
Complete Interrupt Flag, TRNIF (U1IR<3>).
18.4.3
RECEIVING AN OUT TOKEN IN
DEVICE MODE
1. Attach to a USB host and enumerate as
described in “Chapter 9 of the USB 2.0
Specification”.
2. Create a data buffer with the amount of data you
are expecting from the host.
3. In the appropriate (even or odd) TX BD for the
desired endpoint:
a) Set up the status register (BDnSTAT) with
the correct data toggle (DATA0/1) value and
the byte count of the data buffer.
b) Set up the address register (BDnADR) with
the starting address of the data buffer.
c) Set the UOWN bit of the status register to
‘1’.
4. When the USB module receives an OUT token,
it automatically receives the data sent by the
host to the buffer. Upon completion, the module
updates the status register (BDnSTAT) and sets
the Transfer Complete Interrupt Flag, TRNIF
(U1IR<3>).
18.5 Host Mode Operation
The following sections describe how to perform common
Host mode tasks. In Host mode, USB transfers are
invoked explicitly by the host software. The host
software is responsible for the Acknowledge portion of
the transfer. Also, all transfers are performed using the
Endpoint 0 Control register (U1EP0) and Buffer
Descriptors.
18.5.1
ENABLE HOST MODE AND
DISCOVER A CONNECTED DEVICE
1. Enable Host mode by setting the HOSTEN bit
(U1CON<3>). This causes the Host mode con-
trol bits in other USB OTG registers to become
available.
2. Enable the D+ and D- pull-down resistors by set-
ting the DPPULDWN and DMPULDWN bits
(U1OTGCON<5:4>). Disable the D+ and D-
pull-up resistors by clearing the DPPULUP and
DMPULUP bits (U1OTGCON<7:6>).
3. At this point, SOF generation begins with the
SOF counter loaded with 12,000. Eliminate
noise on the USB by clearing the SOFEN bit
(U1CON<0>) to disable Start-Of-Frame packet
generation.
4. Enable the device attached interrupt by setting
the ATTACHIE bit (U1IE<6>).
5. Wait for the device attached interrupt
(U1IR<6> = 1). This is signaled by the USB
device changing the state of D+ or D- from ‘0’
to ‘1’ (SE0 to J state). After it occurs, wait
100 ms for the device power to stabilize.
6. Check the state of the JSTATE and SE0 bits in
U1CON. If the JSTATE bit (U1CON<7>) is ‘0’,
the connecting device is low speed. If the con-
necting device is low speed, set the low
LSPDEN and LSPD bits (U1ADDR<7> and
U1EP0<7>) to enable low-speed operation.
7. Reset the USB device by setting the USBRST
bit (U1CON<4>) for at least 50 ms, sending
Reset signaling on the bus. After 50 ms,
terminate the Reset by clearing USBRST.
8. In order to keep the connected device from
going into suspend, enable the SOF packet
generation by setting the SOFEN bit.
9. Wait 10 ms for the device to recover from Reset.
10. Perform enumeration as described by “Chapter 9
of the USB 2.0 Specification”.
DS39969B-page 250
 2010 Microchip Technology Inc.