PIC24FJ256DA210 Datasheet, PDF(144/408 Page) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

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PIC24FJ256DA210 Datasheet, PDF (144/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

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PIC24FJ256DA210 FAMILY

REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)

bit 10-8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

NOSC<2:0>: New Oscillator Selection bits(1)

111 = Fast RC Oscillator with Postscaler (FRCDIV)

110 = Fast RC/16 Oscillator

101 = Low-Power RC Oscillator (LPRC)

100 = Secondary Oscillator (SOSC)

011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010 = Primary Oscillator (XT, HS, EC)

001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)

000 = Fast RC Oscillator (FRC)

CLKLOCK: Clock Selection Lock Enabled bit

If FSCM is enabled (FCKSM1 = 1):

1 = Clock and PLL selections are locked

0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is disabled (FCKSM1 = 0):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

IOLOCK: I/O Lock Enable bit(2)

1 = I/O lock is active

0 = I/O lock is not active

LOCK: PLL Lock Status bit(3)

1 = PLL module is in lock or PLL module start-up timer is satisfied

0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled

Unimplemented: Read as â0â

CF: Clock Fail Detect bit

1 = FSCM has detected a clock failure

0 = No clock failure has been detected

POSCEN: Primary Oscillator Sleep Enable bit

1 = Primary Oscillator continues to operate during Sleep mode

0 = Primary Oscillator is disabled during Sleep mode

SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit

1 = Enable the Secondary Oscillator

0 = Disable the Secondary Oscillator

OSWEN: Oscillator Switch Enable bit

1 = Initiate an oscillator switch to the clock source specified by the NOSC<2:0> bits

0 = Oscillator switch is complete

Note 1:

2:

3:

Reset values for these bits are determined by the FNOSC Configuration bits.

The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In

addition, if the IOL1WAY Configuration bit is â1â, once the IOLOCK bit is set, it cannot be cleared.

Also resets to â0â during any valid clock switch or whenever a non PLL Clock mode is selected.

DS39969B-page 144

ï£ 2010 Microchip Technology Inc.

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