PIC24FJ256DA210 Datasheet, PDF (96/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED)
Interrupt Source
Vector
IVT
Number Address
AIVT
Address
Interrupt Bit Locations
Flag
Enable
Priority
Timer1
3
00001Ah
Timer2
7
000022h
Timer3
8
000024h
Timer4
27
00004Ah
Timer5
28
00004Ch
UART1 Error
65
000096h
UART1 Receiver
11
00002Ah
UART1 Transmitter
12
00002Ch
UART2 Error
66
000098h
UART2 Receiver
30
000050h
UART2 Transmitter
31
000052h
UART3 Error
81
0000B6h
UART3 Receiver
82
0000B8h
UART3 Transmitter
83
0000BAh
UART4 Error
87
0000C2h
UART4 Receiver
88
0000C4h
UART4 Transmitter
89
0000C6h
USB Interrupt
86
0000C0h
Note 1: Not available in 64-pin devices (PIC24FJXXXDAX06).
00011Ah
000122h
000124h
00014Ah
00014Ch
000196h
00012Ah
00012Ch
000198h
000150h
000152h
0001B6h
0001B8h
0001BAh
0001C2h
0001C4h
0001C6h
0001C0h
IFS0<3>
IFS0<7>
IFS0<8>
IFS1<11>
IFS1<12>
IFS4<1>
IFS0<11>
IFS0<12>
IFS4<2>
IFS1<14>
IFS1<15>
IFS5<1>
IFS5<2>
IFS5<3>
IFS5<7>
IFS5<8>
IFS5<9>
IFS5<6>
IEC0<3>
IEC0<7>
IEC0<8>
IEC1<11>
IEC1<12>
IEC4<1>
IEC0<11>
IEC0<12>
IEC4<2>
IEC1<14>
IEC1<15>
IEC5<1>
IEC5<2>
IEC5<3>
IEC5<7>
IEC5<8>
IEC5<9>
IEC5<6>
IPC0<14:12>
IPC1<14:12>
IPC2<2:0>
IPC6<14:12>
IPC7<2:0>
IPC16<6:4>
IPC2<14:12>
IPC3<2:0>
IPC16<10:8>
IPC7<10:8>
IPC7<14:12>
IPC20<6:4>
IPC20<10:8>
IPC20<14:12>
IPC21<14:12>
IPC22<2:0>
IPC22<6:4>
IPC21<10:8>
7.3 Interrupt Control and Status
Registers
The PIC24FJ256DA210 family of devices implements
a total of 40 registers for the interrupt controller:
• INTCON1
• INTCON2
• IFS0 through IFS6
• IEC0 through IEC6
• IPC0 through IPC25 (except IPC14, IPC17 and
IPC24)
• INTTREG
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the Inter-
rupt Nesting Disable (NSTDIS) bit, as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table (AIVT).
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or an external signal
and is cleared via software.
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
The IPCx registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into the Vector
Number (VECNUM<6:0>) and the Interrupt Level
(ILR<3:0>) bit fields in the INTTREG register. The
new interrupt priority level is the priority of the
pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the order of their vector numbers,
as shown in Table 7-2. For example, the INT0 (External
Interrupt 0) is shown as having a vector number and a
natural order priority of 0. Thus, the INT0IF status bit is
found in IFS0<0>, the INT0IE enable bit in IEC0<0>
and the INT0IP<2:0> priority bits in the first position of
IPC0 (IPC0<2:0>).
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers con-
tain bits that control interrupt functionality. The ALU
STATUS register (SR) contains the IPL<2:0> bits
(SR<7:5>). These indicate the current CPU interrupt
priority level. The user can change the current CPU
priority level by writing to the IPL bits.
DS39969B-page 96
 2010 Microchip Technology Inc.