PIC24FJ256DA210 Datasheet, PDF (146/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
REGISTER 8-2: CLKDIV: CLOCK DIVIDER REGISTER (CONTINUED)
bit 5
bit 4
bit 3-0
PLLEN: 96 MHz PLL Enable bit
The 96 MHz PLL must be enabled when the USB or graphics controller module is enabled. This control
bit can be overridden by the PLL96MHZ (Configuration Word 2 <11>) Configuration bit.
1 = Enable the 96 MHz PLL for USB, graphics controller or HSPLL/ECPLL/FRCPLL operation
0 = Disable the 96 MHz PLL
G1CLKSEL: Display Controller Module Clock Select bit
1 = Use the 96 MHz clock as a graphics controller module clock
0 = Use the 48 MHz clock as a graphics controller module clock
Unimplemented: Read as ‘0’
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
2: This setting is not allowed while the USB module is enabled.
REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
—
bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TUN5⁽¹⁾
TUN4⁽¹⁾
TUN3⁽¹⁾
TUN2⁽¹⁾
TUN1⁽¹⁾
TUN0⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits⁽¹⁾
011111 = Maximum frequency deviation
011110 =
·
·
·
000001 =
000000 = Center frequency, oscillator is running at factory calibrated frequency
111111 =
·
·
·
100001 =
100000 = Minimum frequency deviation
Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC
tuning range and may not be monotonic.
DS39969B-page 146
 2010 Microchip Technology Inc.