PIC24FJ256DA210 Datasheet, PDF (320/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
REGISTER 22-26: G1CLUTWR: COLOR LOOK-UP TABLE (CLUT) MEMORY WRITE DATA
REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLUTWR15 CLUTWR14 CLUTWR13 CLUTWR12 CLUTWR11 CLUTWR10 CLUTWR9 CLUTWR8
bit 15
bit 8
R/W-0
CLUTWR7
bit 7
R/W-0
CLUTWR6
R/W-0
CLUTWR5
R/W-0
CLUTWR4
R/W-0
CLUTWR3
R/W-0
CLUTWR2
R/W-0
CLUTWR1
R/W-0
CLUTWR0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
CLUTWR<15:0>: Color Look-up Table Memory Write Data bits
A write to this register triggers a write to the CLUT memory at the address pointed to by the CLUTADR
bits. A word write or a high byte write to this register triggers a write to the CLUT memory at the address
pointed to by CLUTADR. Low byte write to this register will only update the G1CLUTWR<7:0> and no
write to CLUT memory will be triggered. During power-up and power-down of the display, the most
recent data written to this register will be used to control the timing of the GPWR signal. Refer to the
“PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)” for details on
writing entries to the CLUT.
REGISTER 22-27: G1CLUTRD: COLOR LOOK-UP TABLE (CLUT) MEMORY READ DATA REGISTER
R-0, HSC R-0, HSC R-0, HSC R-0, HSC
R-0, HSC
R-0, HSC R-0, HSC R-0, HSC
CLUTRD15 CLUTRD14 CLUTRD13 CLUTRD12 CLUTRD11 CLUTRD10 CLUTRD9 CLUTRD8
bit 15
bit 8
R-0, HSC
CLUTRD7
bit 7
R-0, HSC
CLUTRD6
R-0, HSC
CLUTRD5
R-0, HSC
CLUTRD4
R-0, HSC
CLUTRD3
R-0, HSC
CLUTRD2
R-0, HSC
CLUTRD1
R-0, HSC
CLUTRD0
bit 0
Legend:
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
CLUTRD<15:0>: Color Look-up Table Memory Read Data bits
This register contains the most recent read from the CLUT memory pointed to by the CLUTADR bits
(G1CLUT<7:0>). Reading of the CLUT memory is triggered when the CLUTTRD bit (G1CLUT<9>) goes
from ‘0’ to ‘1’. Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module
(GFX)” for details on reading entries from the CLUT.
DS39969B-page 320
 2010 Microchip Technology Inc.