PIC24FJ256DA210 Datasheet, PDF (309/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
REGISTER 22-5: G1CON3: DISPLAY CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
bit 15
U-0
R/W-0
R/W-0
—
DPPINOE DPPOWER
bit 8
R/W-0
DPCLKPOL
bit 7
R/W-0
DPENPOL
R/W-0
DPVSPOL
R/W-0
R/W-0
R/W-0
DPHSPOL DPPWROE DPENOE
R/W-0
DPVSOE
R/W-0
DPHSOE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Unimplemented: Read as ‘0’
DPPINOE: Display Pin Output Pad Enable bit
DPPINOE is the master output enable and must be set to allow GDBEN<15:0>, DPENOE,
DPPWROE, DPVSOE and DPHSOE to enable the associated pads
1 = Enable display output pads
0 = Disable display output signals as set by GDBEN<15:0>
Pins used by the signals are assigned to the next enabled module that uses the same pins.
For data signals, GDBEN<15:0> can be used to disable or enable specific data signals while
DPPINOE is set.
DPPOWER: Display Power-up Power-Down Sequencer Control bit
Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)”
for details.
1 = Set Display Power Sequencer Control port (GPWR) to ‘1’
0 = Set Power Control Sequencer signal (GPWR) ‘0’
DPCLKPOL: Display Glass Clock (GCLK) Polarity bit
1 = Display latches data on the positive edge of GCLK
0 = Display latches data on the negative edge of GCLK
DPENPOL: Display Enable Signal (GEN) Polarity bit
For TFT mode (DPMODE (G1CON2<2:0>) = 001):
1 = Active-high (GEN)
0 = Active-low (GEN)
For STN mode (DPMODE (G1CON2<2:0>) = 010 or 011):
1 = GEN connects to the shift clock input of the display (Shift Clock mode)
0 = GEN connects to the MOD input of the display (Line/Frame Toggle mode)
DPVSPOL: Display Vertical Synchronization (VSYNC) Polarity bit
1 = Active-high (VSYNC)
0 = Active-low (VSYNC)
DPHSPOL: Display Horizontal Synchronization (HSYNC) Polarity bit
1 = Active-high (HSYNC)
0 = Active-low (HSYNC)
DPPWROE: Display Power-up/Power-Down Sequencer Control port (GPWR) enable bit
1 = GPWR port is enabled (pin controlled by the DPPOWER bit (G1CON3<8>))
0 = GPWR port is disabled (pin can be used as an ordinary I/O)
DPENOE: Display Enable Port Enable bit
1 = GEN port is enabled
0 = GEN port is disabled
 2010 Microchip Technology Inc.
DS39969B-page 309