PIC24FJ256DA210 Datasheet, PDF (155/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
9.0 POWER-SAVING FEATURES
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 10. “Power-Saving Features”
(DS39698). The information in this data
sheet supersedes the information in the
FRM.
The PIC24FJ256DA210 family of devices provides the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. All PIC24F devices manage power
consumption in four different ways:
• Clock Frequency
• Instruction-Based Sleep and Idle modes
• Software Controlled Doze mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption,
while still maintaining critical application features, such
as timing-sensitive communications.
9.1 Clock Frequency and Clock
Switching
PIC24F devices allow for a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by simply
changing the NOSC bits. The process of changing a
system clock during operation, as well as limitations to
the process, are discussed in more detail in Section 8.0
“Oscillator Configuration”.
9.2 Instruction-Based Power-Saving
Modes
PIC24F devices have two special power-saving modes
that are entered through the execution of a special
PWRSAV instruction. Sleep mode stops clock operation
and halts all code execution; Idle mode halts the CPU
and code execution, but allows peripheral modules to
continue operation. The assembly syntax of the
PWRSAV instruction is shown in Example 9-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
When the device exits these modes, it is said to
“wake-up”.
9.2.1 SLEEP MODE
Sleep mode has these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum, provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode since the system
clock source is disabled.
• The LPRC clock will continue to run in Sleep
mode if the WDT is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may
continue to operate in Sleep mode. This includes
items such as the input change notification on the
I/O ports or peripherals that use an external clock
input. Any peripheral that requires the system
clock source for its operation will be disabled in
Sleep mode. Users can opt to make the voltage
regulator enter standby mode on entering Sleep
mode by clearing the VREGS bit (RCON<8>).
This will decrease current consumption but will
add a delay, TVREG, to the wake-up time. For this
reason, applications that do not use the voltage
regulator should set this bit.
The device will wake-up from Sleep mode on any of the
these events:
• On any interrupt source that is individually
enabled
• On any form of device Reset
• On a WDT time-out
On wake-up from sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
EXAMPLE 9-1:
PWRSAV INSTRUCTION
SYNTAX
PWRSAV
PWRSAV
#0 ; Put the device into SLEEP mode
#1 ; Put the device into IDLE mode
 2010 Microchip Technology Inc.
DS39969B-page 155