PIC24FJ256DA210 Datasheet, PDF (354/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
REGISTER 27-6: DEVREV: DEVICE REVISION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 23
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 15
U-0
—
bit 7
U-0
U-0
U-0
R
R
—
—
—
REV3
REV2
Legend: R = Readable bit
U = Unimplemented bit
U-0
—
U-0
—
R
REV1
U-0
—
bit 16
U-0
—
bit 8
R
REV0
bit 0
bit 23-4
bit 3-0
Unimplemented: Read as ‘0’
REV<3:0>: Device revision identifier bits
27.2 On-Chip Voltage Regulator
All PIC24FJ256DA210 family devices power their core
digital logic at a nominal 1.8V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ256DA210 family
incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
The regulator is controlled by the ENVREG pin. Tying VDD
to the pin enables the regulator, which in turn, provides
power to the core from the other VDD pins. When the reg-
ulator is enabled, a low-ESR capacitor (such as ceramic)
must be connected to the VCAP pin (Figure 27-1). This
helps to maintain the stability of the regulator. The recom-
mended value for the filter capacitor (CEFC) is provided in
Section 30.1 “DC Characteristics”.
27.2.1
VOLTAGE REGULATOR
LOW-VOLTAGE DETECTION
When the on-chip regulator is enabled, it provides a
constant voltage of 1.8V nominal to the digital core
logic.
The regulator can provide this level from a VDD of about
2.1V, all the way up to the device’s VDDMAX. It does not
have the capability to boost VDD levels. In order to pre-
vent “brown-out” conditions when the voltage drops too
low for the regulator, the Brown-out Reset occurs. Then
the regulator output follows VDD with a typical voltage
drop of 300 mV.
To provide information about when the regulator
voltage starts reducing, the on-chip regulator includes
a simple Low-Voltage Detect circuit, which sets the
Low-Voltage Detect Interrupt Flag, LVDIF (IFS4<8>).
This can be used to generate an interrupt to trigger an
orderly shutdown.
FIGURE 27-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to VDD):
3.3V⁽¹⁾
PIC24FJXXXDA1/DA2
VDD
ENVREG
CEFC
(10 F typ)
VCAP
VSS
Note 1:
This is a typical operating voltage. Refer to
Section 30.1 “DC Characteristics” for
the full operating ranges of VDD.
27.2.2 ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approx-
imately 10 s for it to generate output. During this time,
designated as TVREG, code execution is disabled.
TVREG is applied every time the device resumes
operation after any power-down, including Sleep mode.
TVREG is determined by the status of the VREGS bit
(RCON<8>) and the WUTSEL Configuration bits
(CW3<11:10>). Refer to Section 30.0 “Electrical
Characteristics” for more information on TVREG.
DS39969B-page 354
 2010 Microchip Technology Inc.