PIC24FJ256DA210 Datasheet, PDF (150/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
FIGURE 8-2:
96 MHz PLL BLOCK
96 MHz PLL
FNOSC<2:0>
PLLDIV<2:0>
Input from
POSC
Input from
FRC
4 MHz or
8 MHz
÷12
÷8
111
÷6
110
÷5
÷4
÷3
÷2
÷1
101
100
011
010
001
000
4 MHz Branch
96 MHz
PLL
96 MHz Branch
Graphics Clock
Option 1
USB Clock
÷2
48 MHz Clock
for USB Module
System Clock
÷8
÷ 4 ¹¹
÷ 2 ¹⁰
÷3
÷ 1 ⁰¹
00
PLL Output for
System Clock
CPDIV<1:0>
Graphics Clock
÷2
48 MHz Branch
Graphics Clock
Option 2
G1CLKSEL
0
1
÷ 64
÷ 63
...
÷ 17.50
÷ 17.00
...
÷ 1.25
127
126
...
65
64
...
1
÷1 ₀
.
.
GCLKDIV<6:0>.
Clock Output for
Display Interface
(DISPCLK)
Clock Output
for Graphics
Controller
Module (G1CLK)
8.5.1 SYSTEM CLOCK GENERATION
The system clock is generated from the 96 MHz branch
using a configurable postscaler/divider to generate a
range of frequencies for the system clock multiplexer.
The output of the multiplexer is further passed through
a fixed divide-by-3 divider and the final output is used
as the system clock. Figure 8-2 shows this logic in the
system clock sub-block. Since the source is a 96 MHz
signal, the possible system clock frequencies are listed
in Table 8-2. The available system clock options are
always the same, regardless of the setting of the
PLLDIV Configuration bits.
TABLE 8-2: SYSTEM CLOCK OPTIONS FOR 96 MHz PLL BLOCK
MCU Clock Division
(CPDIV<1:0>)
System Clock Frequency
(Instruction Rate in MIPS)
Note 1:
None (00)
32 MHz (16)
2 (01)
4 (10)
8 (11)
16 MHz (8)
8 MHz (4)⁽¹⁾
4 MHz (2)⁽¹⁾
These options are not compatible with USB operation. They may be used whenever the PLL branch is
selected and the USB module is disabled.
DS39969B-page 150
 2010 Microchip Technology Inc.