PIC24FJ256DA210 Datasheet, PDF (306/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
22.1 GFX Module Registers
REGISTER 22-1: G1CMDL: GPU COMMAND LOW REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCMD15
GCMD14
GCMD13
GCMD12 GCMD11
bit 15
R/W-0
GCMD10
R/W-0
GCMD9
R/W-0
GCMD8
bit 8
R/W-0
GCMD7
bit 7
R/W-0
GCMD6
R/W-0
GCMD5
R/W-0
GCMD4
R/W-0
GCMD3
R/W-0
GCMD2
R/W-0
GCMD1
R/W-0
GCMD0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
GCMD<15:0>: Low GPU Command bits
The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). Writes to this register
will not trigger the loading of GCMD <31:0> to the command FIFO. For command FIFO loading, see
the G1CMDH register description.
REGISTER 22-2: G1CMDH: GPU COMMAND HIGH REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCMD31
GCMD30
GCMD29
GCMD28 GCMD27
bit 15
R/W-0
GCMD26
R/W-0
GCMD25
R/W-0
GCMD24
bit 8
R/W-0
GCMD23
bit 7
R/W-0
GCMD22
R/W-0
GCMD21
R/W-0
GCMD20
R/W-0
R/W-0
R/W-0
GCMD19 GCMD18 GCMD17
R/W-0
GCMD16
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
GCMD<31:16>: High GPU Command bits
The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). A word write to the
G1CMDH register triggers the loading of GCMD<31:0> to the command FIFO. Byte writes to the
G1CMDH are allowed but only a high byte write will trigger the command loading to the FIFO. Low
byte write to this register will only update the G1CMDH<7:0> bits.
DS39969B-page 306
 2010 Microchip Technology Inc.