PIC24FJ256DA210 Datasheet, PDF (310/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
REGISTER 22-5: G1CON3: DISPLAY CONTROL REGISTER 3 (CONTINUED)
bit 1
DPVSOE: Display Vertical Synchronization Port Enable bit
1 = VSYNC port is enabled
0 = VSYNC port is disabled
bit 0
DPHSOE: Display Horizontal Synchronization Port Enable bit
1 = HSYNC port is enabled
0 = HSYNC port is disabled
REGISTER 22-6: G1STAT: GFX STATUS REGISTER
R-0, HSC
U-0
U-0
U-0
U-0
U-0
U-0
PUBUSY
—
—
—
—
—
—
bit 15
U-0
—
bit 8
R-0, HSC
IPUBUSY
bit 7
R-0, HSC R-0, HSC
RCCBUSY CHRBUSY
R-0, HSC
VMRGN
R-0, HSC
HMRGN
R-0, HSC
CMDLV
R-0, HSC
CMDFUL
R-0, HSC
CMDMPT
bit 0
Legend:
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PUBUSY: Processing Units are Busy Status bit
This bit is logically equivalent to the ORed combination of IPUBUSY, RCCBUSY or CHRBUSY.
1 = At least one processing unit is busy
0 = None of the processing units are busy
Unimplemented: Read as ‘0’
IPUBUSY: Inflate Processing Unit Busy Status bit
1 = IPU is busy
0 = IPU is not busy
RCCBUSY: Rectangle Copy Graphics Processing Unit Busy Status bit
1 = RCCGPU is busy
0 = RCCGPU is not busy
CHRBUSY: Character Graphics Processing Unit Busy Status bit
1 = CHRGPU is busy
0 = CHRGPU is not busy
VMRGN: Vertical Blanking Status bit
1 = Display interface is in the vertical blanking period
0 = Display interface is not in the vertical blanking period
HMRGN: Horizontal Blanking Status bit
1 = Display interface is in the horizontal blanking period
0 = Display interface is not in the horizontal blanking period
CMDLV: Command Watermark Level Status bit
The number of commands in the command FIFO changed from equal (=) to the command watermark
value to less than (<) the Command Watermark value set in CMDWMK (G1CON1<12:8>) register bits.
1 = Command in FIFO is less than the set CMDWMK value
0 = Command in FIFO is equal to or greater than the set CMDWMK value
CMDFUL: Command FIFO Full Status bit
1 = Command FIFO is full
0 = Command FIFO is not full
CMDMPT: Command FIFO Empty Status bit
1 = Command FIFO is empty
0 = Command FIFO is not empty
DS39969B-page 310
 2010 Microchip Technology Inc.