PIC24FJ256DA210 Datasheet, PDF (351/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
REGISTER 27-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)
bit 4
IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been
completed
bit 3-2
Reserved: Always maintain as ‘1’
bit 1-0
POSCMD<1:0>: Primary Oscillator Configuration bits
11 = Primary oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected
REGISTER 27-3: CW3: FLASH CONFIGURATION WORD 3
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
WPEND
bit 15
R/PO-1
WPCFG
R/PO-1
WPDIS
R/PO-1
ALTPMP⁽¹⁾
R/PO-1
WUTSEL1
R/PO-1
WUTSEL0
R/PO-1
SOSCSEL1
R/PO-1
SOSCSEL0
bit 8
R/PO-1
WPFP7
bit 7
R/PO-1
WPFP6
R/PO-1
WPFP5
R/PO-1
WPFP4
R/PO-1
WPFP3
R/PO-1
WPFP2
R/PO-1
WPFP1
R/PO-1
WPFP0
bit 0
Legend:
R = Readable bit
-n = Value at POR
PO = Program-Once bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-16
bit 15
bit 14
bit 13
bit 12
Note 1:
2:
3:
Unimplemented: Read as ‘1’
WPEND: Segment Write Protection End Page Select bit
1 = Protected code segment upper boundary is at the last page of program memory; the lower
boundary is the code page specified by WPFP<7:0>
0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper
boundary is the code page specified by WPFP<7:0>
WPCFG: Configuration Word Code Page Write Protection Select bit
1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected⁽³⁾
0 = Last page and Flash Configuration Words are write-protected, provided WPDIS = ‘0’
WPDIS: Segment Write Protection Disable bit
1 = Segmented code protection is disabled
0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and
WPFPx Configuration bits
ALTPMP: Alternate EPMP Pin Mapping bit⁽¹⁾
1 = EPMP pins are in default location mode
0 = EPMP pins are in alternate location mode
Unimplemented in 64-pin devices, maintain at ‘1’.
Ensure that the SCLKI pin is made a digital input while using this configuration, see Table 10-1.
Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word’s page,
the Configuration Word’s page is protected.
 2010 Microchip Technology Inc.
DS39969B-page 351