PIC24FJ256DA210 Datasheet, PDF (318/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
REGISTER 22-23: G1VSYNC: VERTICAL SYNCHRONIZATION CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VSLEN7
VSLEN6
VSLEN5
VSLEN4
VSLEN3
VSLEN2
VSLEN1
bit 15
R/W-0
VSLEN0
bit 8
R/W-0
VSST7
bit 7
R/W-0
VSST6
R/W-0
VSST5
R/W-0
VSST4
R/W-0
VSST3
R/W-0
VSST2
R/W-0
VSST1
R/W-0
VSST0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7-0
VSLEN<7:0>: VSYNC Pulse-Width Configuration bits (in lines)
The DPVSOE bit (G1CON3<1>) must be set for the VSYNC signal to toggle; minimum value is 1.
VSST<7:0>: VSYNC Start Delay Configuration bits (in lines)
This is the number of lines from the start of vertical blanking to the start of VSYNC active.
REGISTER 22-24: G1DBLCON: DISPLAY BLANKING CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VENST7
VENST6
VENST5
VENST4
VENST3
VENST2
VENST1
bit 15
R/W-0
VENST0
bit 8
R/W-0
HENST7
bit 7
R/W-0
HENST6
R/W-0
HENST5
R/W-0
HENST4
R/W-0
HENST3
R/W-0
HENST2
R/W-0
HENST1
R/W-0
HENST0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7-0
VENST<7:0>: Vertical Blanking Start to First Displayed Line Configuration bits (in lines)
This is the number of lines from the start of vertical blanking to the first displayed line of a frame.
HENST<7:0>: Horizontal Blanking Start to First Displayed Pixel Configuration bits (in DISPCLKs)
This is the number of GCLK cycles from the start of horizontal blanking to the first displayed pixel of
each displayed line.
DS39969B-page 318
 2010 Microchip Technology Inc.