PIC24FJ256DA210 Datasheet, PDF (356/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
27.3.1 WINDOWED OPERATION
The Watchdog Timer has an optional Fixed-Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (CW1<6>) to ‘0’.
FIGURE 27-2:
SWDTEN
FWDTEN
LPRC Input
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode
WDT BLOCK DIAGRAM
LPRC Control
FWPSA
31 kHz
Prescaler
(5-bit/7-bit)
WDT
Counter
1 ms/4 ms
27.3.2 CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN Control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
WDTPS<3:0>
Postscaler
1:1 to 1:32.768
Wake from Sleep
WDT Overflow
Reset
DS39969B-page 356
 2010 Microchip Technology Inc.