PIC24FJ256DA210 Datasheet, PDF (25/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
64-Pin
TQFP/QFN
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
Description
PGEC1
PGED1
PGEC2
PGED2
PGEC3
PGED3
PMA0
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMA16
PMA17
PMA18
PMA19
PMA20
PMA21
PMA22
PMACK1
PMACK2
PMALL
PMALH
PMALU
PMBE0
PMBE1
PMCS1
PMCS2
Legend:
Note 1:
2:
3:
4:
15
24
K1
I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming Clock 1.
16
25
K2
I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 1.
17
26
L1
I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 2.
18
27
J3
I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 2.
11
20
H1
I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 3.
12
21
H2
I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 3.
—
44
L8
I/O ST Parallel Master Port Address bit 0 Input (Buffered Slave
modes) and Output (Master modes).
—
43
K7
I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
—
14
F3
O
—
—
12, 60⁽¹⁾ F2, G11⁽¹⁾ O
—
—
11,59⁽¹⁾
F4,G10⁽¹⁾ O
—
—
10,40⁽¹⁾
E3,K6⁽¹⁾
O
—
—
29
K3
O
—
—
28
L2
O
—
—
50
L11
O
—
—
49
L10
O
—
—
42
L7
O
—
—
41
J7
O
—
—
35
J5
O
— Parallel Master Port Address bits<22:2>.
—
34
L5
O
—
—
71
C11
O
—
—
70
D11
O
—
—
95
C4
O
—
—
92
B5
O
—
—
40,10⁽¹⁾
K6,E3⁽¹⁾
O
—
—
19
G2
O
—
—
59, 11⁽¹⁾ G10, F4⁽¹⁾ O
—
—
60,12⁽¹⁾
G11,F2⁽¹⁾ O
—
—
66,9⁽¹⁾
E11,E1⁽¹⁾ O
—
—
77
A10
I ST/TTL Parallel Master Port Acknowledge Input 1.
—
69
E10
I ST/TTL Parallel Master Port Acknowledge Input 2.
—
44
L8
O
— Parallel Master Port Lower Address Latch Strobe.
—
43
K7
O
— Parallel Master Port Higher Address Latch Strobe.
—
14
F3
O
— Parallel Master Port Upper Address Latch Strobe.
—
78
B9
O
— Parallel Master Port Byte Enable Strobe 0.
—
67
E8
O
— Parallel Master Port Byte Enable Strobe 1.
—
71⁽³⁾,18
C11⁽³⁾,G1 I/O ST/TTL Parallel Master Port Chip Select Strobe 1.
—
70⁽²⁾,9,
66⁽¹⁾
D11⁽²⁾,E1, O
E11⁽¹⁾
— _{Parallel Master Port Chip Select Strobe 2.}
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I²C™ = I²C/SMBus input buffer
The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’.
The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
 2010 Microchip Technology Inc.
DS39969B-page 25