PIC24FJ256DA210 Datasheet, PDF (91/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type
Clock Source
SYSRST Delay
System Clock
Delay
Notes
POR⁽⁷⁾
EC
TPOR + TSTARTUP + TRST
—
1, 2, 3
ECPLL
TPOR + TSTARTUP + TRST
TLOCK
1, 2, 3, 5
XT, HS, SOSC
TPOR + TSTARTUP + TRST
TOST
1, 2, 3, 4
XTPLL, HSPLL
TPOR + TSTARTUP + TRST
TOST + TLOCK 1, 2, 3, 4, 5
FRC, FRCDIV
TPOR + TSTARTUP + TRST
TFRC
1, 2, 3, 6, 7
FRCPLL
TPOR + TSTARTUP + TRST
TFRC + TLOCK 1, 2, 3, 5, 6
LPRC
TPOR + TSTARTUP + TRST
TLPRC
1, 2, 3, 6
BOR
EC
TSTARTUP + TRST
—
2, 3
ECPLL
TSTARTUP + TRST
TLOCK
2, 3, 5
XT, HS, SOSC
TSTARTUP + TRST
TOST
2, 3, 4
XTPLL, HSPLL
TSTARTUP + TRST
TOST + TLOCK 2, 3, 4, 5
FRC, FRCDIV
TSTARTUP + TRST
TFRC
2, 3, 6, 7
FRCPLL
TSTARTUP + TRST
TFRC + TLOCK 2, 3, 5, 6
LPRC
TSTARTUP + TRST
TLPRC
2, 3, 6
MCLR
Any Clock
TRST
—
3
WDT
Any Clock
TRST
—
3
Software
Any clock
TRST
—
3
Illegal Opcode Any Clock
TRST
—
3
Uninitialized W Any Clock
TRST
—
3
Trap Conflict Any Clock
TRST
—
3
Note 1: TPOR = Power-on Reset delay (10 s nominal).
2: TSTARTUP = TVREG (10 s nominal when VREGS = 1 and when VREGS = 0; depends upon
WUTSEL<1:0> bits setting).
3: TRST = Internal State Reset time (32 s nominal).
4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
5: TLOCK = PLL lock time.
6: TFRC and TLPRC = RC Oscillator start-up times.
7: If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC
so the system clock delay is just TFRC, and in such cases, FRC start-up time is valid. It switches to the
primary oscillator after its respective clock delay.
6.3.1
POR AND LONG OSCILLATOR
START-UP TIMES
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
6.3.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
 2010 Microchip Technology Inc.
DS39969B-page 91