PIC24FJ256DA210 Datasheet, PDF (90/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
6.1 Special Function Register Reset
States
Most of the Special Function Registers (SFRs) associ-
ated with the PIC24F CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed
values of the FNOSC bits in Flash Configuration
Word 2 (CW2) (see Table 6-2). The RCFGCAL and
NVMCON registers are only affected by a POR.
6.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 6-3. Note that the system Reset
signal, SYSRST, is released after the POR delay time
expires.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The Fail-Safe Clock Monitor (FSCM) delay determines
the time at which the FSCM begins to monitor the
system clock source after the SYSRST signal is
released.
6.3 Clock Source Selection at Reset
If clock switching is enabled, the system clock source
at device Reset is chosen, as shown in Table 6-2. If
clock switching is disabled, the system clock source is
always selected according to the oscillator Configura-
tion bits. Refer to the “PIC24F Family Reference
Manual”, Section 8.0 “Oscillator Configuration” for
further details.
TABLE 6-2:
Reset Type
POR
BOR
MCLR
WDTO
SWR
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
FNOSC Configuration bits
(CW2<10:8>)
COSC Control bits
(OSCCON<14:12>)
DS39969B-page 90
 2010 Microchip Technology Inc.