PIC24FJ256DA210 Datasheet, PDF (317/408 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)

PIC24FJ256DA210 FAMILY
REGISTER 22-21: G1ACTDA: ACTIVE DISPLAY AREA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACTLINE7 ACTLINE6 ACTLINE5 ACTLINE4 ACTLINE3 ACTLINE2
bit 15
R/W-0
ACTLINE1
R/W-0
ACTLINE0
bit 8
R/W-0
ACTPIX7
bit 7
R/W-0
ACTPIX6
R/W-0
ACTPIX5
R/W-0
ACTPIX4
R/W-0
ACTPIX3
R/W-0
ACTPIX2
R/W-0
ACTPIX1
R/W-0
ACTPIX0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7-0
ACTLINE<7:0>: Number of Lines Before the First Active (Displayed) Line bits
Typically, ACTLINEx = VENSTx (G1DBLCON<15:8>).
This register is added for versatility in the timing of the active lines.
For TFT mode, DPMODE bits (G1CON2<2:0>) = 001; the minimum value is 2.
For STN mode, DPMODE bits (G1CON2<2:0>) = 010,011,100; the minimum value is 0.
ACTPIX<7:0>: Number of Pixels Before the First Active (Displayed) Pixel bits (in DISPCLKs)
Typically, ACTPIXx = HENSTx (G1DBLCON<7:0>).
This register is added for versatility in the timing of the active pixels. Note that the programmed value
is computed in DISPCLK cycles. This value is dependent on the DPGWDTH bit (G1CON2<15:14>).
Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)”
for details.
REGISTER 22-22: G1HSYNC: HORIZONTAL SYNCHRONIZATION CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HSLEN7
HSLEN6
HSLEN5
HSLEN4
HSLEN3
HSLEN2
HSLEN1
HSLEN0
bit 15
bit 8
R/W-0
HSST7
bit 7
R/W-0
HSST6
R/W-0
HSST5
R/W-0
HSST4
R/W-0
HSST3
R/W-0
HSST2
R/W-0
HSST1
R/W-0
HSST0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7-0
HSLEN<7:0>: HSYNC Pulse-Width Configuration bits (in DISPCLKs)
DPHSOE bit (G1CON3<0>) must be set for the HSYNC signal to toggle; minimum value is 1.
HSST<7:0>: HSYNC Start Delay Configuration bits (in DISPCLKs)
This is the number of DISPCLK cycles from the start of horizontal blanking to the start of HSYNC active.
 2010 Microchip Technology Inc.
DS39969B-page 317