S9S12G128F0CLF Datasheet, PDF (648/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Timer Module (TIM16B8CV3)
20.3.2.19 Precision Timer Prescaler Select Register (PTPSR)
R
W
Reset
7
PTPS7
0
6
PTPS6
5
PTPS5
4
PTPS4
3
PTPS3
2
PTPS2
1
PTPS1
0
0
0
0
0
0
Figure 20-29. Precision Timer Prescaler Select Register (PTPSR)
0
PTPS0
0
Read: Anytime
Write: Anytime
All bits reset to zero.
...
Table 20-23. PTPSR Field Descriptions
Field
Description
7:0
PTPS[7:0]
Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.
These are effective only when the PRNT bit of TSCR1 is set to 1. Table 20-24 shows some selection examples
in this case.
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter
stages equal zero.
The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit:
PRNT = 1 : Prescaler = PTPS[7:0] + 1
PTPS7
0
0
0
0
-
-
-
0
0
0
-
-
-
1
Table 20-24. Precision Timer Prescaler Selection Examples when PRNT = 1
PTPS6
0
0
0
0
-
-
-
0
0
0
-
-
-
1
PTPS5
0
0
0
0
-
-
-
0
0
0
-
-
-
1
PTPS4
0
0
0
0
-
-
-
1
1
1
-
-
-
1
PTPS3
0
0
0
0
-
-
-
0
0
0
-
-
-
1
PTPS2
0
0
0
0
-
-
-
0
1
1
-
-
-
1
PTPS1
0
0
1
1
-
-
-
1
0
0
-
-
-
0
PTPS0
0
1
0
1
-
-
-
1
0
1
-
-
-
0
Prescale
Factor
1
2
3
4
-
-
-
20
21
22
-
-
-
253
MC9S12G Family Reference Manual, Rev.1.10
648
Freescale Semiconductor