S9S12G128F0CLF Datasheet, PDF (398/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Analog-to-Digital Converter (ADC10B12CV2)
Address Name
R
0x0024 ATDDR10
W
R
0x0026 ATDDR11
W
0x0028 - Unimple- ^R
0x002F mented W
Bit 7
0
6
5
4
3
2
1
See Section 12.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 12.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 12.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 12.3.2.12.2, “Right Justified Result Data (DJM=1)”
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-2. ADC10B12C Register Summary (Sheet 3 of 3)
Bit 0
0
12.3.2 Register Descriptions
This section describes in address order all the ADC10B12C registers and their individual bits.
12.3.2.1 ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence.
Module Base + 0x0000
R
W
Reset
7
Reserved
0
Read: Anytime
6
5
4
3
2
0
0
0
WRAP3
WRAP2
0
0
0
1
1
= Unimplemented or Reserved
Figure 12-3. ATD Control Register 0 (ATDCTL0)
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Table 12-1. ATDCTL0 Field Descriptions
Field
Description
1
WRAP1
1
0
WRAP0
1
3-0
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
WRAP[3-0] multi-channel conversions. The coding is summarized in Table 12-2.
Table 12-2. Multi-Channel Wrap Around Coding
WRAP3 WRAP2 WRAP1 WRAP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting
Reserved¹
AN1
AN2
AN3
AN4
AN5
MC9S12G Family Reference Manual, Rev.1.10
398
Freescale Semiconductor