S9S12G128F0CLF Datasheet, PDF (608/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Serial Peripheral Interface (S12SPIV5)
SPPR2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 19-6. Example SPI Baud Rate Selection (25 MHz Bus Clock)
SPPR1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SPPR0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SPR2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SPR1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud Rate
Divisor
56
112
224
448
896
1792
16
32
64
128
256
512
1024
2048
Baud Rate
446.43 kbit/s
223.21 kbit/s
111.61 kbit/s
55.80 kbit/s
27.90 kbit/s
13.95 kbit/s
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
97.66 kbit/s
48.83 kbit/s
24.41 kbit/s
12.21 kbit/s
19.3.2.4 SPI Status Register (SPISR)
7
6
5
4
3
2
1
0
R SPIF
0
SPTEF
MODF
0
0
0
0
W
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-6. SPI Status Register (SPISR)
Read: Anytime
Write: Has no effect
Table 19-7. SPISR Field Descriptions
Field
7
SPIF
Description
SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For
information about clearing SPIF Flag, please refer to Table 19-8.
0 Transfer not yet complete.
1 New data copied to SPIDR.
MC9S12G Family Reference Manual, Rev.1.10
608
Freescale Semiconductor