S9S12G128F0CLF Datasheet, PDF (306/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12S Debug Module (S12SDBG)
Field2 Bits in Normal and Loop1 Modes
Bit 3
Bit 2
Bit 1
Bit 0
CSD
CVA
PC17
PC16
Figure 8-26. Information Bits PCH
Bit
3
CSD
2
CVA
1
PC17
0
PC16
Table 8-38. PCH Field Descriptions
Description
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored
address is a source or destination address. This bit has no meaning in Compressed Pure PC mode.
0 Source Address
1 Destination Address
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector
address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set.
This bit has no meaning in Compressed Pure PC mode .
0 Non-Vector Destination Address
1 Vector Destination Address
Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17.
Program Counter bit 16— In Normal and Loop1 mode this bit corresponds to program counter bit 16.
8.4.5.4
Trace Buffer Organization (Compressed Pure PC mode)
Table 8-39. Trace Buffer Organization Example (Compressed PurePC mode)
Mode
Line ^2-bits
Number _{Field 3}
Line 1 00
Line 2 11
Compressed ^{Line 3 01}
Pure PC Mode _{Line 4 00}
Line 5 10
Line 6 00
6-bits
Field 2
PC4
0
0
6-bits
Field 1
PC1 (Initial 18-bit PC Base Address)
PC3
0
PC6 (New 18-bit PC Base Address)
PC8
PC9 (New 18-bit PC Base Address)
6-bits
Field 0
PC2
PC5
PC7
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