S9S12G128F0CLF Datasheet, PDF (121/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Port Integration Module (S12GPIMV1)
NOTE
If there is more than one signal associated with a pin, the priority is indicated
by the position in the table from top (highest priority) to bottom (lowest
priority).
Port Pin
Signal
Table 2-4. Signals and Priorities
Signals per Device and Package
(signal priority on pin from top to bottom)
Legend
■ Signal available on pin
❍ Routing option on pin
❏ Routing reset location
Not available on pin
I/O
Description
100
64
48
32
20
-
BKGD
MODC
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ I MODC input during
RESET
BKGD ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ I/O BDM communication
A PA7-PA0 [PA7:PA0] ■ ■ ■
I/O GPIO
B PB7-PB6 [PB7:PB6] ■ ■ ■
I/O GPIO
PB5
XIRQ
■■■
I Non-maskable
level-sensitive interrupt
[PB5]
■■■
I/O GPIO
PB4
IRQ
■■■
I Maskable level- or
falling-edge sensitive
interrupt
[PB4]
■■■
I/O GPIO
PB3
[PB3]
■■■
I/O GPIO
PB2
ECLKX2 ■ ■ ■
O Free-running clock
(ECLK x 2)
[PB2]
■■■
I/O GPIO
PB1 API_EXTCLK ❏ ❏ ❏
O API Clock
[PB1]
■■■
I/O GPIO
PB0
ECLK ■ ■ ■
O Free-running clock
[PB0]
■■■
I/O GPIO
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
121