S9S12G128F0CLF Datasheet, PDF (45/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

1.7.2.21 CAN signals
Device Overview MC9S12G-Family
1.7.2.21.1 RXCAN Signal
This signal is associated with the receive functionality of the scalable controller area network controller
(MSCAN).
1.7.2.21.2 TXCAN Signal
This signal is associated with the transmit functionality of the scalable controller area network controller
(MSCAN).
1.7.2.22 PWM[7:0] Signals
The signals PWM[7:0] are associated with the PWM module outputs.
1.7.2.23 Internal Clock outputs
1.7.2.23.1 ECLK
This signal is associated with the output of the divided bus clock (ECLK).
NOTE
This feature is only intended for debug purposes at room temperature.
It must not be used for clocking external devices in an application.
1.7.2.23.2 ECLKX2
This signal is associated with the output of twice the bus clock (ECLKX2).
NOTE
This feature is only intended for debug purposes at room temperature.
It must not be used for clocking external devices in an application.
1.7.2.23.3 API_EXTCLK
This signal is associated with the output of the API clock (API_EXTCLK).
1.7.2.24 IOC[7:0] Signals
The signals IOC[7:0] are associated with the input capture or output compare functionality of the timer
(TIM) module.
1.7.2.25 IRQ
This signal is associated with the maskable IRQ interrupt.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
45