S9S12G128F0CLF Datasheet, PDF (221/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

5V Analog Comparator (ACMPV1)
Table 3-2. ACMPC Register Field Descriptions (continued)
Field
Description
3-2
ACMOD
[1:0]
ACMP Mode—
Selects the type of compare event setting ACIF.
00 Flag setting disabled
01 Comparator output rising edge
10 Comparator output falling edge
11 Comparator output rising or falling edge
0
ACE
ACMP Enable—
This bit enables the ACMP module and takes it into normal mode (see Section 3.5, “Modes of Operation”). This bit
also connects the related input pins with the module’s low pass input filters. When the module is not enabled, it
remains in low power shutdown mode.
Note: After setting ACE=1 an initialization delay of 63 bus clock cycles must be accounted for. During this time the
comparator output path to all subsequent logic (ACO, ACIF, timer link, excl. ACMPO) is held at its current state.
When resetting ACE to 0 the current state of the comparator will be maintained.
0 ACMP disabled
1 ACMP enabled
3.6.2.2 ACMP Status Register (ACMPS)
Address 0x0261
7
6
5
4
3
2
R
ACO
0
0
0
0
ACIF
W
Reset
0
0
0
0
0
0
Figure 3-4. ACMP Status Register (ACMPS)
1 _{Read: Anytime}
Write:
ACIF: Anytime, write 1 to clear
ACO: Never
Access: User read/write¹
1
0
0
0
0
0
Field
7
ACIF
6
ACO
Table 3-3. ACMPS Register Field Descriptions
Description
ACMP Interrupt Flag—
ACIF is set when a compare event occurs. Compare events are defined by ACMOD[1:0]. Writing a logic “1” to the
bit field clears the flag.
0 Compare event has not occurred
1 Compare event has occurred
ACMP Output—
Reading ACO returns the current value of the synchronized ACMP output. Refer to ACE description to account for
initialization delay on this path.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
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